(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method and package for thermally improved Plastic Ball Grid Array (PBGA) packaging.
(2) Description of the Prior Art
The semiconductor industry has since its inception achieved improvements in the performance of semiconductor devices by device miniaturization and by increasing the device packaging density.
One of the original approaches that has been used to create surface mounted, high pin count integrated circuit packages has been the use of the Quad Flat Pack (QFP) with various pin configurations. For the QFP, closely spaced leads along the four edges of the flat package are used for making electrical connections from where the electrical connections are distributed to the surrounding circuitry. The input/output (I/O) connections that can be made to the QFP are therefore confined to the edges of the flat package, which limits the number of I/O connections that can be made to the QFP even in applications where the pin to pin spacing is small. The QFP has found to be cost effective for semiconductor devices where the device I/O pin count does not exceed 200. To circumvent this limitation, a new package, a Ball Grid Array (BGA) package has been introduced. For the BGA package, the electrical contact points are distributed over the entire bottom surface of the package thereby eliminating the restriction of having I/O connects only around the periphery of the package. More contact points with greater spacing between the contact points can therefore be allocated across the BGA package than was the case with the QFP. The contact points that are used for the BGA package are typically solder balls that have the added advantage of facilitating flow soldering of the package onto a printed circuit board.
Prior Art substrate packaging uses ceramic and plastic BGA packaging. Ceramic substrate packaging is expensive and has proven to limit the performance of the overall package. Recent years have seen the emergence of plastic BGA packaging; this packaging has become the main stream design and is frequently used in high volume BGA package fabrication. The Plastic BGA (PBGA) package performs satisfactorily when used for low-density flip-chip IC""s. If the number of pins emanating from the IC is high, that is in excess of 350 pins, or if the number of pins coming from the IC is less than 350 but the required overall package size is small, or if the chip power dissipation is high (in excess of 4 Watts per chip), the plastic structure becomes complicated and expensive.
The invention addresses concerns of thermal performance of the PBGA package that in addition provides advantages of electrical performance (such as low parasitic inductance being added by the package) and advantages of assembly (such as low cost, being a flexible solution that does not require a redesign of the substrate over which the die is mounted) while the package meets conventional manufacturing standards.
U.S. Pat. No. 5,872,396 (Fujimoto) shows a heat spreader using a mold compound and a mold cavity.
U.S. Pat. No. 5,641,987 (Lee) shows another similar heat spreader design.
U.S. Pat. No. 5,977,626 (Want et al.) U.S. Pat. No. 6,201,301 (Hoang) and U.S. Pat. No. 5,834,839 (Mertol) show related heat spreaders and methods.
A principle objective of the invention is to provide a Plastic BGA package of improved thermal performance.
Another objective of the invention is to provide an integrated circuit package of enhanced electrical performance.
Another objective of the invention is to provide an integrated circuit package of a structure that can be maintained as the current standard Plastic Ball Grid Array package format.
In accordance with the objectives of the invention a new method and package is provided for face-up packaging of semiconductor devices. The semiconductor device is mounted over the surface of a semiconductor device mounting support using conventional methods of device packaging up through device bond wire interconnect to electrical traces on the surface of the semiconductor device mounting support over which the device is mounted. An internal mold cap is formed over the device, the internal mold cap has an opening exposing the surface of the device. An external mold cap is formed surrounding the internal mold cap, with a cavity separating the external mold cap from the internal mold cap. Thermally conductive epoxy is deposited in the opening of the internal mold cap and in the cavity between the internal and the external mold cap. A heat spreader is placed and attached after which a thermal epoxy and mold cure is applied to the package. The package is further completed by the application of contact balls to a first surface of the semiconductor device mounting support, the semiconductor device has been mounted over a second surface of the semiconductor device mounting support.